1. Technical Field
The application relates generally to semiconductor devices in wide-bandgap semiconductor materials and, in particular, to diodes (including Schottky barrier diodes and bipolar junction diodes) made in silicon carbide (SiC) and to structures that monolithically integrate these diodes, including structures having mesa edge termination.
2. Background of the Technology
Monolithic devices comprising Schottky and PiN diodes are known (See, for example, U.S. Pat. No. 6,861,723 and [1]). U.S. Pat. No. 6,573,128 discloses a SiC Junction Barrier Schottky (JBS)/Merged P-I-N Schottky (MPS) grid that is formed of Schottky metal deposited on p-type islands defined by plasma etching through an epitaxially grown layer. However, this structure is unable to effectively protect itself from a surge current because of the absence of p-type ohmic contacts on the p-type regions and insufficient conductivity modulation caused by low doping of p-type regions.
U.S. Pat. Nos. 6,104,043 and 6,524,900 disclose JBS/MPS diodes having heavily doped p-type regions formed by ion implantation. If ohmic contacts to heavily doped implanted p-type regions are formed as disclosed in U.S. Pat. No. 6,104,043, however, the conductivity modulation in the drift region of such a structure suffers from low minority carrier lifetime caused by residual implantation damage even after thermal anneal at high temperature.
U.S. Pat. No. 4,982,260 describes the definition of p-type emitter regions by etching through the heavily doped p-type well created by diffusion. However, since diffusion of dopants into SiC occurs very slowly at even extremely high temperatures, as a practical matter, a p-type well can only be formed in n-type SiC by ion implantation, which has the disadvantage described above.
U.S. Pat. No. 6,897,133 describes forming p-type emitter regions by etching trenches in n-type material and filling them with p-type epitaxially grown material followed by chemical-mechanical polishing or another planarization step. This device, however, has JFET regions that may significantly limit current conduction under normal operating conditions.
SiC devices that employ mesa edge termination are also known [2]. Mesa edge termination technology for Si, however, is generally inapplicable to SiC device technology due to difficulties related to etching of SiC and removing the damage caused by the etching process (See, for example, U.S. Pat. No. 5,449,925 and [3]). The use of mesa termination in 4H—SiC diodes has also been disclosed (U.S. Pat. No. 6,897,133, [4], and [5]).
There still exists a need for semiconductor devices having improved properties.